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HANBit
HMD4M32M8EG/8EAG
16Mbyte(4Mx32) 72-pin EDO MODE, 2K/4K Ref. SIMM Design 5V Part No. HMD4M32M8EG, HMD4M32M8EAG
GENERAL DESCRIPTION
The HMD4M32M8E is a 4M x 32 bit dynamic RAM high-density memory module. The module consists of eight CMOS 4M x 4bit DRAMs in 24-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
w Part Identification HMD4M32M8EG-- 2048 Cycles/32ms Ref. Gold HMD4M32M8EAG-- 4096 Cycles/64ms Ref. Gold w Access times : 50, 60ns w High-density 16MByte design. w Single + 5V 0.5V power supply w JEDEC standard pinout w EDO(extended data out) mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 SYMBOL Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ22 DQ7 DQ23 A7 A11 Vcc A8 A9 NC /RAS2 NC NC NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /WE NC PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC Vss PD2 PD3 PD4 NC Vss
PIN ASSIGNMENT
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
-5 -6 M
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4 50ns Vss NC Vss Vss 60ns Vss NC NC NC
PERFORMANCE RANGE
A0-A11:Address Input (4K Ref.) Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tHPC A0-A10:Address Input (2K Ref.) 26ns *Note: A11 is used for only HMD4M32M8EAG 30ns
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FUNCTIONAL BLOCK DIAGRAM
HMD4M32M8EG/8EAG
/CAS0 /RAS0
CAS RAS OE W
U1
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ0-DQ3
CAS RAS OE W
U2
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ4-DQ7
/CAS1
CAS RAS OE W
U4
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ8-DQ11
CAS RAS OE W
U5
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ12-DQ15
/CAS2
/RAS2
CAS RAS OE W
U6
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ16-DQ19
CAS RAS OE W
U7
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ20-DQ23
/CAS3
CAS RAS OE W
U8
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ24-DQ27
CAS RAS OE W
U9
DQ0 DQ1 DQ2 A0-A10(A11) DQ3
DQ28-DQ31
/WE A0-A10(A11)
Vcc Vss
0.1uFor0.22uFCapacitor foreachDRAM To all DRAMs
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD4M32M8EG/8EAG
RATING -1V to 7.0V -1V to 7.0V 8W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 -6 ICC2 -5 ICC3 -6 -5 ICC4 -6 ICC5 -5 ICC6 -6 Il(L) IO(L) VOH -40 -5 2.4 800 40 5 0.4 mA A A V V 800 8 880 mA mA mA 800 880 mA mA 800 16 880 mA mA mA SPEED -5 MIN MAX 880 UNITS mA
VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min )
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HMD4M32M8EG/8EAG
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
o
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/WE) Input Capacitance (/RAS0,/RAS2) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
MIN -
MAX 64 70 42 30 17
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 -6 UNIT MIN MAX MIN 110 50 13 25 3 3 2 30 50 13 38 8 20 15 5 0 10 0 10K 37 25 10K 13 50 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10K 45 30 10K 15 50 60 15 30 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 90
STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay from /CAS Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time
SYMBOL tRC tRAC tCAC tAA tCLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
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Column address hold time Column address hold referenced to /RAS Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced to /RAS Refresh period Write command set-up time /CAS to /W delay time /RAS to /W delay time /CAS precharge(C-B-R counter test) Column address to /W delay time Access time from /CAS precharge /CAS precharge time (Hyper Page cycle) /RAS pulse width (Hyper Page cycle) /WE to /RAS precharge time (C-B-R refresh) tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tCWD tRWD tCPT tAWD tCPA tCP tRASP tWRP 8 50 10 0 36 73 20 48 8 40 25 0 0 0 10 40 10 13 8 0 8 40
HMD4M32M8EG/8EAG
10 45 30 0 0 0 10 45 10 15 10 0 10 45 32 0 40 85 20 55 30 10 200K 60 10 200K 35 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
/WE to /RAS hold time (C-B-R refresh) tWRH 10 10 ns NOTES 1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC. 5.Assumes that tRCD tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
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HMD4M32M8EG/8EAG
TIMING DIAGRAM
Please refer to attached timing diagram chart (IV)
PACKAGING INFORMATION
SIMM Design
107.95 mm 3.38 mm
R 1.57 mm 101.19 mm
3.18 mm DIA 0.51 mm
16.00 6.35
2.03 mm 10.16 mm
1 72
1.02 mm
6.35
95.25 mm
1.27 mm
3.34 mm
6.35 mm
0.25 mm MAX
2.54 mm
MIN
1.270.08 mm Gold : 1.040.10 mm
1.27
Solder:0.9140.10mm
ORDERING INFORMATION
Refresh Cycle 2,048 Cycles 32ms Ref. 4,096 Cycle 64ms Ref. 2,048 Cycles 32ms Ref. 4,096 Cycle 64ms Ref.
Part Number
Density
Org.
Package
Vcc
Speed
HMD4M32M8EG-5 HMD4M32M8EAG-5 HMD4M32M8EG-6 HMD4M32M8EAG-6
16MByte 16MByte 16MByte 16MByte
4MX 32bit 4MX 32bit 4MX 32bit 4MX 32bit
72 Pin-SIMM 72 Pin-SIMM 72 Pin-SIMM 72 Pin-SIMM
5.0V 5.0V 5.0V 5.0V
50ns 50ns 60ns 60ns
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